Field effect type semiconductor device


PURPOSE:To block the leakage of holes from a p-channel layer effectively, by providing a semiconductor layer, which has high p type impurity concentration and the width of a narrow forbidden band in comparison with a semiconductor layer wherein a source electrode, a drain electrode and a gate electrode are provided. CONSTITUTION:A required power source is connected across a first electrode 41 as a source electrode and a second electrode 42 as a drain electrode. Under this state, a control voltage is applied across the first electrode 41 and a third electrode 43 as a gate electrode. Then a current, which is controlled in correspondence with the value of the control voltage can be supplied to a load. Holes from a p-channel layer 55, which is formed on the side of a second semiconductor layer 22 between first and second semiconductor regions 31 and 32 tend to leak to the outside through the semiconductor layer 22, a fourth semiconductor layer 24 and the electrode 42. Since the semiconductor layer 22 has the broad width of the forbidden band, the leakage can be effectively blocked. When the p type impurity concentration and the thickness of the semiconductor layer 24 are changed, the threshold voltage can be set in the desired range.




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Patent Citations (1)

    Publication numberPublication dateAssigneeTitle
    JP-S613465-AJanuary 09, 1986Fujitsu LtdSemiconductor device

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Cited By (6)

    Publication numberPublication dateAssigneeTitle
    FR-2690276-A1October 22, 1993Picogiga SaIC with complementary heterojunction field effect transistors
    JP-S61267358-ANovember 26, 1986Hitachi LtdSemiconductor device
    JP-S63190387-AAugust 05, 1988Texas Instruments IncComplementary hetero-structure field effect transistor and manufacture of the same
    US-5060031-AOctober 22, 1991Motorola, IncComplementary heterojunction field effect transistor with an anisotype N+ ga-channel devices
    US-5192701-AMarch 09, 1993Kabushiki Kaisha ToshibaMethod of manufacturing field effect transistors having different threshold voltages
    US-5510635-AApril 23, 1996Picogiga Societe AnonymeIntegrated circuit having complementary heterojunction field effect transistors